`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:22:15 11/11/2014
// Design Name:   BaudRateGenerator
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/Xilin/uart-arquitectura-2014/bAUD.v
// Project Name:  UART
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: BaudRateGenerator
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module bAUD;

	// Inputs
	reg clock;
	reg reset;

	// Outputs
	wire tick;

	// Instantiate the Unit Under Test (UUT)
	BaudRateGenerator uut (
		.reset(reset),
		.clock(clock), 
		.tick(tick)
	);

	initial begin
		// Initialize Inputs
		clock = 0;
		// Wait 100 ns for global reset to finish
		#100;
		reset = 1;
		#100;
      reset = 0; 
		// Add stimulus here

	end
always begin
#1;
clock = ~clock;
end
      
endmodule

